M6MGD13TW66CWG-P Datasheet, PDF (1/3 Pages) Renesas Technology Corp – 134,217,728-BIT (8,388,608-WORD BY 16-BIT) CMOS FLASH MEMORY & 67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS MOBILE RAM

Preliminary
Notice: This is not a final specification.
Some parametric limits are subject to change.
Renesas LSIs
M6MGD13TW66CWG-P
134,217,728-BIT (8,388,608-WORD BY 16-BIT) CMOS FLASH MEMORY &
67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS MOBILE RAM
Stacked-CSP ( Chip Scale Package)
Description
The M6MGD13TW66CWG-P is suitable for a high
The M6MGD13TW66CWG-P is a Stacked Chip Scale
performance cellular phone and a mobile PC that are
Package (S-CSP) that contents 128M-bit Flash memory and required to be small mounting area, weight and small power
64M-bit Mobile RAM in a 72-pin Stacked CSP with leaded dissipation.
solder ball.
128M-bit Flash memory is a 8,388,608 words, single power
supply and high performance non-volatile memory fabricated
Features
Access Time
Random Access/ Page Access
by CMOS technology for the peripheral circuit and DINOR IV
Flash
70ns /25ns (Max.)
(Divided bit-line NOR IV) architecture for the memory cell. All
memory blocks are locked and can not be programmed or
Mobile RAM 85ns /25ns (Max.)
erased, when F-WP# is Low. Using Software Lock Release Supply Voltage
FM-VCC=2.7 ~ 3.0V
function, program or erase operation can be executed.
Ambient Temperature
Ta= -40 ~ 85 degree
64M-bit Mobile RAM is a 4,194,304 words high density RAM
fabricated by CMOS technology for the peripheral circuit and
Package
72pin S-CSP,
DRAM cell for the memory array. The interface is compatible to
Ball pitch 0.80mm
an asynchronous SRAM.
Outer-ball:Sn-Pb
The cells are automatically refreshed and the refresh control is _Application
not required for system. The device also has the partial block
refresh scheme and the power down mode by writing the
Mobile communication products
command.
PIN CONFIGURATION (TOP VIEW)
INDEX(Laser Marking)
1234 5678
DU
DU _A
DU
DU _B
NC
A18
M-
LB#
F-
WP#
GND
F-
WE#
C ^{A16 A20}
A5
A17
M-
UB#
NC
F-
RP#
F-
RY/BY#
A8
D ^A11
A4 A7
E ^M-
OE#
A19
DU
A21
A10 A15
F ^{A0 A6 DU DQ11 DU NC A9 A14}
F-
CE1#
A3
G ^{DQ9 DU DQ12 DQ13 DQ15 A13}
GND A2
F-
OE#
A1
H ^{DQ8 DQ10 NC DQ6}
M-
WE#
A12
J ^{DQ0 DQ2 NC DQ4 DQ14 GND}
F-
CE2#
M-
CE#
K ^{DQ1 DQ3}
FM-
VCC
DQ5
DQ7
DU
DU
DU _L
DU
(Top View)
DU _M
FM-VCC : VCC for Flash / Mobile RAM
GND
: GND for Flash / Mobile RAM
A0-A21 : Common address for Flash/Mobile RAM
DQ0-DQ15 : Data I/O
F-CE1# : Flash chip enable 1
F-CE2# : Flash chip enable 2
F-OE#
: Output enable for Flash Memory
F-WE# : Write enable for Flash Memory
8.5 mm
F-RP# : Reset power down for Flash
F-WP# : Write protect for Flash
F-RY/BY# : Flash Memory Ready /Busy
M-CE# : Mobile RAM chip enable
M-OE# : Output enable for Mobile RAM
M-WE# : Write enable for Mobile RAM
M-LB# : Lower byte control for Mobile RAM
M-UB#
NC
: Upper byte control for Mobile RAM
: Non Connection
DU
: Don’t Use
1
Rev.1.0.48a_bezb