M6MGB331S4BKT Datasheet, PDF (1/3 Pages) Renesas Technology Corp – 33,554,432-BIT (2,097,152 - WORD BY 16-BIT/4,194,304-WORD BY 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (262,144-WORD BY 16-BIT/524,288-WORD B

Preliminary
Notice: This is not a final specification.
Some parametric limits are subject to change.
Renesas LSIs
M6MGB/T331S4BKT
33,554,432-BIT (2,097,152 - WORD BY 16-BIT/4,194,304-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT/524,288-WORD BY 8-BIT) CMOS SRAM
Stacked - µ MCP (micro Multi Chip Package)
Description
The M6MGB/T331S4BKT is a Stacked micro Multi Chip
Package (S- µMCP) that contents 32M-bit Flash memory and
4M-bit Static RAM in a 52-pin TSOP for lead free use.
32M-bit Flash memory is a 4,194,304 bytes / 2,097,152 words,
3.3V-only, and high performance non-volatile memory
fabricated by CMOS technology for the peripheral circuit and
DINOR (Divided bit-line NOR) architecture for the memory cell.
4M-bit SRAM is a 524,288 bytes / 262,144 words
asynchronous SRAM fabricated by silicon-gate CMOS
technology.
M6MGB/T331S4BKT is suitable for the application of the
mobile-communication-system to reduce both the mount
space and weight.
M6MGB/T331S4BKT provides for Software Lock Release
function. Usually, all memory blocks are locked and can not
be programmed or erased, when F-WP# is low. Using
Software Lock Release function, program or erase operation
can be executed.
Features
Access Time Flash
70ns (Max.)
SRAM
70ns (Max.)
Supply Voltage
VCC=2.7 ~ 3.0V
Ambient Temperature
Ta=-40 ~ 85 °C
Package
52pin TSOP(Type-II),
Application
Lead pitch 0.4mm
Outer-lead finishing:Sn-Cu
Mobile communication products
A15
A14
A13
A12
A11
A10
A9
A8
A19
S-CE1#
WE#
F-RP#
F-WP#
S-VCC
S-CE2
DU
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
PIN CONFIGURATION (TOP VIEW)
1
52
2
51
3
50
4
49
5
48
6
47
7
46
8
45
9
44
10
43
11
42
12
41
13
14
M6MGB/T331S4BKT
40
39
15
38
16
37
17
36
18
35
19
34
20
33
21
32
22
31
23
30
24
29
25
28
26
27
A16
BYTE#
S-UB#
GND
S-LB#
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
F-VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
F-CE#
A0
10.49 mm
Outline 52PTJ-A
F-VCC
S-VCC
GND
A-1-A17
A18-A20
DQ0-DQ15
F-CE#
S-CE#,S-CE2
OE#
WE#
:Vcc for Flash
:Vcc for SRAM
:GND for Flash/SRAM
:Flash/SRAM common Address
:Address for Flash
:Data I/O
:Flash Chip Enable
:SRAM Chip Enable
:Flash/SRAM Output Enable
:Flash/SRAM Write Enable
F-WP#
F-RP#
F-RY/BY#
BYTE#
S-LB#
S-UB#
DU
:Flash Write Protect
:Flash Reset Power Down
:Flash Ready/Busy
:Flash/SRAM Byte Enable
:SRAM Lower Byte
:SRAM Upper Byte
:Do not use
1
Rev.0.1_48a_beez