M66281FP Datasheet, PDF (1/16 Pages) Mitsubishi Electric Semiconductor – 5120 x 8-BIT x 2 LINE MEMORY

M66281FP
5120 × 8-Bit × 2 Line Memory
REJ03F0254-0200
Rev.2.00
Sep 14, 2007
Description
The M66281FP is high speed line memory that uses high performance silicon gate CMOS process technology and
adopts the FIFO (First In First Out) structure consisting of 5120 words × 8 bits × 2.
Since memory is available to simultaneously output 1 line delay and 2 line delay data, the M66281FP is optimal for the
compensation of data of multiple lines.
Features
• Memory configuration:
5120 words × 8 bits × 2 (dynamic memory)
• High speed cycle:
25 ns (Min)
• High speed access:
18 ns (Max)
• Output hold:
3 ns (Min)
• Reading and writing operations can be completely carried out independently and asynchronously
• Variable length delay bit
• Input/output:
TTL direct connection allowable
• Output:
3 states
• Q00 to Q07:
1 line delay
• Q10 to Q17:
2 line delay
Application
Digital copying machine, laser beam printer, high speed facsimile, etc.
Block Diagram
Data inputs
D0 to D7
31 30 29 28 27 23 22 21
Data outputs
Q0 to Q7
Data outputs
Q10 to Q17
45 46 47 2 3 4 5 6 9 10 11 12 13 16 17 18
Input buffer
Output buffer
WEB ³⁶
Write
enable input
WRESB 35
Write
reset input
WCK ³⁴
Write
clock input
V_CC 8
V_{CC 19}
V_CC 32
V_CC 44
Memory array
5120 words × 8 bits × 2
( ) Memory only for 1 line delay data
Memory only for 2 line delay data
42 REB
Read
enable input
41 RRESB
Read
reset input
40 RCK
Read
clock input
7 GND
20 ^GND
33 GND
43 GND
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
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