M66257FP Datasheet, PDF (1/13 Pages) Mitsubishi Electric Semiconductor – 5120 x 8-BIT x 2 LINE MEMORY (FIFO)

M66257FP
5120 × 8-Bit × 2 Line Memory (FIFO)
REJ03F0251-0200
Rev.2.00
Sep 14, 2007
Description
The M66257FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word × 8-bit double
configuration which uses high-performance silicon gate CMOS process technology.
It allows simultaneous output of 1-line delay data and 2-line delay data, and is most suitable for data correction over
multiple lines.
It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between
devices with different data processing throughput.
Features
• Memory configuration:
5120 words × 8 bits × 2 (dynamic memory)
• High-speed cycle:
25 ns (Min)
• High-speed access:
18 ns (Max)
• Output hold:
3 ns (Min)
• Fully independent, asynchronous write and read operations
• Output:
3 states
• Q₀₀ to Q₀₇:
• Q₁₀ to Q₁₇:
1-line delay
2-line delay
Application
Digital photocopiers, high-speed facsimile, laser beam printers.
Block Diagram
Data input
D₀ to D₇
27 26 25 24 23 22 21 20
Data output
Q₀₀ to Q₀₇
Data output
Q₁₀ to Q₁₇
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Input buffer
Output buffer
WE ³²
Write
enable input
WRES 31
Write
reset input
WCK 30
Write
clock input
V_CC 18
V_{CC 28}
V_CC 36
Memory array of
5120-word × 8-bit × 2 configuration
( ) 1-line delay data only memory/
2-line delay data only memory
35 RE
Read
enable input
34 RRES
Read
reset input
33 RCK
Read
clock input
1 GND
19 GND
29 GND
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
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