HM64YGB36100 Datasheet, PDF (1/21 Pages) Renesas Technology Corp – 32M Synchronous Late Write Fast Static RAM (1-Mword × 36-bit)

HM64YGB36100 Series
32M Synchronous Late Write Fast Static RAM
(1-Mword × 36-bit)
REJ03C0271-0100
(Previous ADE-203-1374 (Z) Rev. 0.0)
Rev.1.00
Jun.27.2005
Description
The HM64YGB36100 is a synchronous fast static RAM organized as 1-Mword × 36-bit. It has realized high speed
access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most
appropriate for the application which requires high speed, high density memory and wide bit width configuration, such
as cache and buffer memory in system. It is packaged in standard 119-bump BGA.
Note: All power supply and ground pins must be connected for proper operation of the device.
Features
• 2.5 V ± 5% operation and 1.5 V (V_DDQ)
• 32-Mbit density
• Synchronous register to register operation
• Internal self-timed late write
• Byte write control (4 byte write selects, one for each 9-bit)
• Optional ×18 configuration
• HSTL compatible I/O
• Programmable impedance output drivers
• Differential HSTL clock inputs
• Asynchronous G output control
• Asynchronous sleep mode
• FC-BGA 119pin package with SRAM JEDEC standard pinout
• Limited set of boundary scan JTAG IEEE 1149.1 compatible
Ordering Information
Type No.
Organization Access time Cycle time
Package
HM64YGB36100BP-33 1M × 36
1.6 ns
3.3 ns
119-bump 1.27 mm
14 mm × 22 mm BGA
PRBG0119DC-A (BP-119F)
Note: HM: Hitachi Memory prefix, 64: External Cache SRAM, Y: VDD = 2.5 V, G: Late Write SRAM, B: VDDQ = 1.5 V
Rev.1.00 Jun 27, 2005 page 1 of 19