HD74SSTV16859 Datasheet, PDF (1/11 Pages) Renesas Technology Corp – 1:2 13-bit SSTL_2 Registered Buffer

HD74SSTV16859
1:2 13-bit SSTL_2 Registered Buffer
REJ03D0832-0900
(Previous: ADE-205-337H)
Rev.9.00
Apr 07, 2006
Description
The HD74SSTV16859 is a 1:2 13-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset
(RESET) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to QA, QB is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on
the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise margins.
When RESET is low, all registers are reset and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low
state during power up.
Features
• Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input
• Differential SSTL_2 (Stub series terminated logic) CLK signal
• Flow through architecture optimizes PCB layout
• Ordering Information
Part Name
Package Type
HD74SSTV16859TEL TSSOP-64 pin
Package Code
(Previous code)
PTSP0064KA-A
(TTP-64DV)
Package
Abbreviation
T
Taping Abbreviation
(Quantity)
EL (1,000 pcs / Reel)
Function Table
Inputs
RESET
CLK
CLK
D
QA
L
X
X
X
L
H
↓
↑
H
H
H
↓
↑
L
L
H
L or H
H or L
X
Q₀ ^*1
H : High level
L : Low level
X : Immaterial
↑ : Low to high transition
↓ : High to low transition
Note: 1. Output level before the indicated steady state input conditions were established.
Outputs
QB
L
H
L
Q₀ ^*1
Rev.9.00 Apr 07, 2006 page 1 of 10