HD74SSTV16857B Datasheet, PDF (1/16 Pages) Renesas Technology Corp – 1:1 14-bit SSTL_2 Registered Buffer

HD74SSTV16857B
1:1 14-bit SSTL_2 Registered Buffer
REJ03D0023–0100Z
(Previous ADE-205-712 (Z))
Rev.1.00
Jun.03.2003
Description
The HD74SSTV16857B is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and
LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET. Data is
triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to
maintain noise margins. When RESET is low, all registers are reset and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
Features
• Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input
• Differential SSTL_2 (Stub series terminated logic) CLK signal
• Flow through architecture optimizes PCB layout
• Ordering Information
Part Name
Package Type
Package Code Package
Abbreviation
HD74SSTV16857BTEL TSSOP-48 pin TTP-48DBV T
HD74SSTV16857BNEL TVSOP-48 pin TTP-48DEV N
Note: Please consult the sales office for the above package availability.
Taping
Abbreviation (Quantity)
EL (1,000 pcs / Reel)
EL (1,000 pcs / Reel)
Rev.1.00, Jun.03.2003, page 1 of 16