HD74SSTV16857A Datasheet, PDF (1/11 Pages) Renesas Technology Corp – 1:1 14-bit SSTL_2 Registered Buffer

HD74SSTV16857A
1:1 14-bit SSTL_2 Registered Buffer
REJ03D0831-0100
(Previous: ADE-205-695)
Rev.1.00
Apr 07, 2006
Description
The HD74SSTV16857A is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset
(RESET) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on the
positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise margins.
When RESET is low, all registers are reset and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low
state during power up.
Features
• Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input
• Differential SSTL_2 (Stub series terminated logic) CLK signal
• Flow through architecture optimizes PCB layout
• Ordering Information
Part Name
Package Type
Package Code
(Previous code)
HD74SSTV16857ATEL TSSOP-48 pin
PTSP0048KA-A
T
(TTP-48DBV)
HD74SSTV16857ANEL TVSOP-48 pin
PTSP0048LA-A
N
(TTP-48DEV)
Note: Please consult the sales office for the above package availability.
Package
Abbreviation
Taping Abbreviation
(Quantity)
EL (1,000 pcs / Reel)
EL (1,000 pcs / Reel)
Function Table
H:
L:
X:
↑:
↓:
Note:
Inputs
RESET
CLK
CLK
D
L
X
X
X
H
↓
↑
H
H
↓
↑
L
H
L or H
H or L
X
High level
Low level
Immaterial
Low to high transition
High to low transition
1. Output level before the indicated steady state input conditions were established.
Output Q
L
H
L
Q₀ ^*1
Rev.1.00 Apr 07, 2006 page 1 of 10