HD74LVC74 Datasheet, PDF (1/7 Pages) Hitachi Semiconductor – Dual D-type Flip Flops with Preset and Clear

HD74LVC74
Dual D-type Flip Flops with Preset and Clear
Description
REJ03D0347–0400Z
(Previous ADE-205-066C (Z))
Rev.4.00
Jul. 22, 2004
The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic
level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset
and clear are independent of the clock and accomplished by a low level at the appropriate input. Low voltage and high-
speed operation is suitable at the battery drive product (note type personal computer) and low power consumption
extends the life of a battery for long time operation.
Features
• V_CC = 2.0 V to 5.5 V
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.0 V (@V_CC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@V_CC = 3.0 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
HD74LVC74FPEL
SOP–14 pin (JEITA) FP–14DAV
HD74LVC74TELL
TSSOP–14 pin
TTP–14DV
Note: Please consult the sales office for the above package availability.
Package
Abbreviation
FP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
Outputs
PR
CLR
CK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H ^*1
H ^*1
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q₀
Q₀
H
H
H
X
Q₀
Q₀
H
H
↓
X
Q₀
Q₀
H: High level
L: Low level
X: Immaterial
↓ : High to Low transition
↑ : Low to high transition
Q₀: Level to Q before the indicated steady input conditions was established.
Note: 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if preset and
clear go high simultaneously.
Rev.4.00 Jul. 22, 2004 page 1 of 6