HD74LVC125A Datasheet, PDF (1/7 Pages) Hitachi Semiconductor – Quad. Bus Buffer Gates with 3-state Outputs

HD74LVC125A
Quad. Bus Buffer Gates with 3-state Outputs
REJ03D0348–0400Z
(Previous ADE-205-108C (Z))
Rev.4.00
Jul. 23, 2004
Description
The HD74LVC125A has four bus buffer gates in a 14 pin package. The device require the three state control input C to
be taken high to put the output into the high impedance condition, whereas the device requires the control input to be
low to put the output into high impedance. Low voltage and high-speed operation is suitable at the battery drive
product (note type personal computer) and low power consumption extends the life of a battery for long time operation.
Features
• V_CC = 2.0 V to 5.5 V
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• All outputs V_OUT (Max.) = 5.5 V (@V_CC = 0 V or output off state)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.0 V (@V_CC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@V_CC = 3.0 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
HD74LVC125AFPEL
SOP–14 pin (JEITA) FP–14DAV
HD74LVC125ATELL
TSSOP–14 pin
TTP–14DV
Note: Please consult the sales office for the above package availability.
Package
Abbreviation
FP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
C
A
H
X
L
L
L
H
H: High level
L: Low level
X: Immaterial
Z: High impedance
Outputs Y
Z
L
H
Rev.4.00 Jul. 23, 2004 page 1 of 6