HD74LV74A Datasheet, PDF (1/10 Pages) Hitachi Semiconductor – Dual D-type Flip Flops with Preset and Clear

HD74LV74A
Dual D–type Flip Flops with Preset and Clear
REJ03D0312–0300Z
(Previous ADE-205-244A (Z))
Rev.3.00
Jun. 02, 2004
Description
The HD74LV74A has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The input
data is transferred to the output at the rising edge of clock pulse CLK. Low-voltage and high-speed operation is
suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the
battery life.
Features
• V_CC = 2.0 V to 5.5 V operation
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• All outputs V_O (Max.) = 5.5 V (@V_CC = 0 V)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.3 V (@V_CC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@V_CC = 3.0 V to 3.6 V), ±12 mA (@V_CC = 4.5 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
HD74LV74AFPEL
SOP–14 pin(JEITA) FP–14DAV
FP
HD74LV74ARPEL
SOP–14 pin(JEDEC) FP–14DNV
RP
HD74LV74ATELL
TSSOP–14 pin
TTP–14DV
T
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
Outputs
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H*¹
H*¹
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
↓
X
Q₀
Q₀
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
Q₀: The level of Q immediately before the input conditions shown in the above table is determined.
1.: Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset
and Clear go HIGH simultaneously.
Rev.3.00 Jun. 02, 2004 page 1 of 9