HD74LV573A Datasheet, PDF (1/9 Pages) Hitachi Semiconductor – Octal D-type Transparent Latches with 3-state Outputs

HD74LV573A
Octal D-type Transparent Latches with 3-state Outputs
Description
REJ03D0519–0100
Rev.1.00
Feb. 01, 2005
The HD74LV573A has eight D type latches with three state outputs in a 20 pin package. When the latch enables input
is high, the Q outputs will follow the D inputs. When the latch enables goes low, data at the D inputs will be retained at
the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all
outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the
storage elements. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
• V_CC = 2.0 V to 5.5 V operation
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• All outputs V_O (Max.) = 5.5 V (@V_CC = 0 V)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.3 V (@V_CC = 3.3 V, Ta = 25°C)
• Output current ±8 mA (@V_CC = 3.0 V to 3.6 V), ±16 mA (@V_CC = 4.5 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
Package
(Previous Code) Abbreviation
HD74LV573AFPEL
SOP–20 pin (JEITA) PRSP0020DD–B
FP
(FP–20DAV)
HD74LV573ATELL
TSSOP–20 pin
PTSP0020JB–A
T
(TTP–20DAV)
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
OE
LE
D
H
X
X
L
H
L
L
H
H
L
L
X
Note: H: High level
L: Low level
X: Immaterial
Z: High impedance
Q₀: Output level before the indicated steady state input conditions were established.
Output Q
Z
L
H
Q₀
Rev.1.00 Feb.01.2005 page 1 of 8