HD74LV1G126A Datasheet, PDF (1/12 Pages) Renesas Technology Corp – Bus Buffer Gate with 3-state Output

HD74LV1G126A
Bus Buffer Gate with 3–state Output
REJ03D0072–0600Z
(Previous ADE-205-324D (Z))
Rev.6.00
Sep.01.2003
Description
The HD74LV1G126A has a bus buffer gate with 3–state output in a 5 pin package. Output is disabled
when the associated output enable (OE) input is low. To ensure the high impedance state during power up
or power down, OE should be connected to V_CC through a pull-down resistor; the minimum value of the
resistor is determined by the current souring capability of the driver. Low voltage and high-speed operation
is suitable for the battery powered products (e.g., notebook computers), and the low power consumption
extends the battery life.
Features
• The basic gate function is lined up as Renesas uni logic series.
• Supplied on emboss taping for high-speed automatic mounting.
• Electrical characteristics equivalent to the HD74LV126A
Supply voltage range : 1.65 to 5.5 V
Operating temperature range : –40 to +85°C
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
All outputs V_O (Max.) = 5.5 V (@V_CC = 0 V, Output : Z)
• Output current ±6 mA (@V_CC = 3.0 V to 3.6 V), ±12 mA (@V_CC = 4.5 V to 5.5 V)
• All the logical input has hysteresis voltage for the slow transition.
• Ordering Information
Part Name
Package Type
Package Code Package
Abbreviation
HD74LV1G126ACME CMPAK–5 pin
CMPAK–5V
CM
CMPAK–5V(O)
HD74LV1G126AVSE VSON–5 pin
TNP–5DV
VS
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
Rev.6.00, Sep.01.2003, page 1 of 11