HD74LV1G125A_08 Datasheet, PDF (1/8 Pages) Renesas Technology Corp – Bus Buffer Gate with 3-state Output

HD74LV1G125A
Bus Buffer Gate with 3–state Output
REJ03D0071-0700
Rev.7.00
Mar 21, 2008
Description
The HD74LV1G125A has a bus buffer gate with 3–state output in a 5 pin package. Output is disabled when the
associated output enable (OE) input is high. To ensure the high impedance state during power up or power down, OE
should be connected to V_CC through a pull-down resistor; the minimum value of the resistor is determined by the current
sourcing capability of the driver. Low voltage and high-speed operation is suitable for the battery powered products
(e.g., notebook computers), and the low power consumption extends the battery life.
Features
• The basic gate function is lined up as Renesas uni logic series.
• Supplied on emboss taping for high-speed automatic mounting.
• Electrical characteristics equivalent to the HD74LV125A
Supply voltage range : 1.65 to 5.5 V
Operating temperature range : –40 to +85°C
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
All outputs V_O (Max.) = 5.5 V (@V_CC = 0 V, Output : Z)
• Output current ±6 mA (@V_CC = 3.0 V to 3.6 V), ±12 mA (@V_CC = 4.5 V to 5.5 V)
• All the logical input has hysteresis voltage for the slow transition.
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
HD74LV1G125ACME
CMPAK–5 pin
PTSP0005ZC-A
(CMPAK-5V)
HD74LV1G125AVSE
VSON–5 pin
PUSN0005KA-A
(TNP-5DV)
Note: Please consult the sales office for the above package availability.
Package
Abbreviation
CM
VS
Taping Abbreviation
(Quantity)
E (3000 pcs/reel)
E (3000 pcs/reel)
Outline and Article Indication
• HD74LV1G125A
Index band
Marking
LB
CMPAK–5
= Control code
REJ03D0071-0700 Rev.7.00, Mar 21, 2008
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