HD74LV126A Datasheet, PDF (1/10 Pages) Hitachi Semiconductor – Quad. Bus Buffer Gates with 3-state Outputs

HD74LV126A
Quad. Bus Buffer Gates with 3-state Outputs
REJ03D0316–0300Z
(Previous ADE-205-259A (Z))
Rev.3.00
Jun. 03, 2004
Description
The HD74LV126A features independent line drivers with three state outputs. Each output is disabled when the
associated output enable (OE) input is low. To ensure the high impedance state during power up or power down, OE
should be connected to GND through a pull-down resistor; the minimum value of the resistor is determined by the
current souring capability of the driver. Low-voltage and high-speed operation is suitable for the battery-powered
products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
• V_CC = 2.0 V to 5.5 V operation
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• All outputs V_O (Max.) = 5.5 V (@V_CC = 0 V)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.3 V (@V_CC = 3.3 V, Ta = 25°C)
• Output current ±8 mA (@V_CC = 3.0 V to 3.6 V), ±16 mA (@V_CC = 4.5 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
HD74LV126AFPEL
SOP–14 pin(JEITA) FP–14DAV
FP
HD74LV126ARPEL
SOP–14 pin(JEDEC) FP–14DNV
RP
HD74LV126ATELL
TSSOP–14 pin
TTP–14DV
T
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
OE
A
H
H
H
L
L
X
Note: H: High level
L: Low level
X: Immaterial
Z: High impedance
Output Y
H
L
Z
Rev.3.00 Jun. 03, 2004 page 1 of 9