HD74LS78A Datasheet, PDF (1/7 Pages) Hitachi Semiconductor – Dual J-K Flip-Flops(with Preset, Common Clear, and Common Clock)

HD74LS78A
Dual J-K Flip-Flops
(with Preset, Common Clear, and Common Clock)
Features
• Ordering Information
REJ03D0419–0300
Rev.3.00
Jul.22.2005
Part Name
Package Type
Package Code Package
(Previous Code) Abbreviation
HD74LS78AFPEL SOP-14 pin (JEITA)
PRSP0014DF-B
(FP-14DAV)
FP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
Pin Arrangement
CK 1
1PR 2
1J 3
V_CC 4
CLR 5
2PR 6
2K 7
K _CK J
CLR PR
Q
Q
K _CK J
CLR PR
Q
Q
14 1K
13 _1Q
12 _1Q
11 _GND
10 _2J
9 _2Q
8 2Q
(Top view)
Function Table
Inputs
Outputs
Preset
Clear
Clock
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H*
H*
H
H
↓
L
L
Q0
Q0
H
H
↓
H
L
H
L
H
H
↓
L
H
L
H
H
H
↓
H
H
Toggle
H
H
H
X
X
Q0
Q0
Notes: H; high level, L; low level, X; irrelevant, ↓; transition from high to low level,
Q0; level of Q before the indicated steady-state input conditions were established.
Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established.
Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓.
* This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level.
Rev.3.00, Jul.22.2005, page 1 of 6