HD74LS77 Datasheet, PDF (1/5 Pages) Hitachi Semiconductor – 4-bit Bistable Latches

HD74LS77
4-bit Bistable Latches
REJ03D0418–0300
Rev.3.00
Jul.22.2005
The HD74LS77 is ideally suited for use as temporary storage for binary information between processing units and
input / output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable
(G) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low,
the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the
enable is permitted to go high.
Features
• Ordering Information
Part Name
Package Type
HD74LS77FPEL SOP-14 pin (JEITA)
Package Code
(Previous Code)
PRSP0014DF-B
(FP-14DAV)
Package
Abbreviation
FP
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
Pin Arrangement
1D 1
2D 2
Enable 3-4 3
V_CC 4
3D 5
4D 6
NC 7
Q
DG
DG
Q
Q
DG
DG
Q
14 1Q
13 _2Q
12 _{Enable 1-2}
11 _GND
10 _NC
9 _3Q
8 4Q
(Top view)
Function Table
Inputs
D
G
L
H
H
H
X
L
H; high level, L; low level, X; irrelevant
Outputs
Q
L
H
Q0
Rev.3.00, Jul.22.2005, page 1 of 4