HD74LS257 Datasheet, PDF (1/6 Pages) Hitachi Semiconductor – Quadruple 2-line-to-1-line Data Selectors/Multiplexers(with non inverted 3-state outputs)

HD74LS257
Quadruple 2-line-to-1-line Data Selectors / Multiplexers
(with not inverted 3-state outputs)
REJ03D0469–0300
Rev.3.00
Jul.15.2005
This multiplexer features three-state outputs that can interface directly with and drive data lines of bus-organized
systems. With all but one of the common outputs disabled (at a high-impedance state) the low impedance of the single
enabled output will drive the bus line to a high or low logic level.
To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output-
enable circuitry is designed such that the output disable times are shorter than the output enable times.
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LS257P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
PRSP0016DH-B
HD74LS257FPEL SOP-16 pin (JEITA)
(FP-16DAV)
FP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
Pin Arrangement
Select 1
1A 2
1B 3
1Y 4
2A 5
2B 6
2Y 7
GND 8
S
1A
OC
1B
4A
1Y
4B
2A
4Y
2B
3A
2Y
3B
3Y
16 V_CC
15 ^Output
Control
14 _4A
13 _4B
12 _4Y
11 _3A
10 _3B
9 _3Y
(Top view)
Rev.3.00, Jul.15.2005, page 1 of 5