HD74LS164 Datasheet, PDF (1/9 Pages) Hitachi Semiconductor – 8-Bit Parallel-Out Serial-In Shift Registers

HD74LS164
8-Bit Parallel-Out Serial-in Shift Register
REJ03D0448–0200
Rev.2.00
Feb.18.2005
This 8-bit shift register features gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit
complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the
first flip-flop to the low level at the next clock pulse. A high-level input enables the other input which will them
determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but
only information meeting the setup requirements will be entered. Clocking occurs on the low-to-high-level transition of
the clock input.
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LS164P
DILP-14 pin
PRDP0014AB-B
P
(DP-14AV)
HD74LS164FPEL SOP-14 pin (JEITA)
PRSP0014DF-B
(FP-14DAV)
FP
PRSP0014DE-A
HD74LS164RPEL SOP-14 pin (JEDEC) _(FP-14DNV)
RP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Pin Arrangement
Serial
Inputs
A1
B2
QA 3
QB 4
Outputs
QC 5
QD 6
GND 7
A
B
QH
QA
QG
QB
QF
QC
QE
QD _CK CLR
(Top view)
14 V_CC
13 _QH
12 _QG
Outputs
11 _QF
10 _QE
9 _Clear
8 _Clock
Rev.2.00, Feb.18.2005, page 1 of 8