HD74LS125A Datasheet, PDF (1/5 Pages) Hitachi Semiconductor – Quadriple Bus Buffer Gates(with three-state outputs)

HD74LS125A
Quadruple Bus Buffer Gates (with three-state outputs)
REJ03D0430–0200
Rev.2.00
Feb.18.2005
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LS125AP
DILP-14 pin
PRDP0014AB-B
P
(DP-14AV)
HD74LS125AFPEL SOP-14 pin (JEITA)
PRSP0014DF-B
(FP-14DAV)
FP
PRSP0014DE-A
HD74LS125ARPEL SOP-14 pin (JEDEC) _(FP-14DNV)
RP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Pin Arrangement
1C 1
1A 2
1Y 3
2C 4
2A 5
2Y 6
GND 7
14 V_CC
13 _4C
12 _4A
11 _4Y
10 _3C
9 _3A
8 3Y
(Top view)
Function Table
Inputs
C
A
H
X
L
L
L
H
Note: H ; high level,
L ; low level,
X ; irrelevant,
Z ; off (high-impedance) state of a 3-state output
Outputs
Y
Z
L
H
Rev.2.00, Feb.18.2005, page 1 of 4