HD74HC4024 Datasheet, PDF (1/7 Pages) Hitachi Semiconductor – 7-stage Binary Counter

HD74HC4024
7-stage Binary Counter
REJ03D0325-0300
Rev.3.00
Mar 30, 2006
Description
The HD74HC4024 is a 7-stage counter. This device is incremented on the falling edge (negative transition) of the input
clock, and all its output is reset to a low level by applying a logical high on its reset input.
Features
• High Speed Operation: t_pd (Clock to Q₁) = 14 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC4024P
DILP-14 pin
PRDP0014AB-B
P
(DP-14AV)
PRSP0014DF-B
HD74HC4024FPEL SOP-14 pin (JEITA)
(FP-14DAV)
FP
PRSP0014DE-A
HD74HC4024RPEL SOP-14 pin (JEDEC)
RP
(FP-14DNV)
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Function Table
Clock
L
L
H
H
Reset
L
H
L
H
L
H
L
H
Outputs State
No change
All outputs are low
No change
All outputs are low
No change
All outputs are low
Advance to next state
All outputs are low
Rev.3.00 Mar 30, 2006 page 1 of 6