HD74HC390 Datasheet, PDF (1/7 Pages) Hitachi Semiconductor – Dual Decade Counters

HD74HC390
Dual Decade Counters
REJ03D0624-0200
(Previous ADE-205-503)
Rev.2.00
Mar 30, 2006
Description
The HD74HC390 incorporate dual decade counters, each composed of a divide-by-two and a divide-by-five counter.
The divide-by-two and divide-by-five counters can be cascaded to form dual decade, dual bi-quinary, or various
combinations up to a single divide-by-100 counter.
The HD74HC390 is incremented on the high to low transition (negative edge) of the clock input, and each has an
independent clear input. When clear is set high all four bits of each counter are set to a low level. This enables count
truncation and allows the implementation of divide-by-N counter configurations.
Features
• High Speed Operation: t_pd (Clock A to Q_A) = 11 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC390P
DILP-16 pin
PRDP0016AE-B
P
(DP-16FV)
HD74HC390FPEL SOP-16 pin (JEITA)
PRSP0016DH-B
FP
(FP-16DAV)
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
Function Table
Note:
Clock
A
B
Clear
X
X
H
X
L
X
L
1. H; High level, L; Low level, X; Irrelevant, Z; High impedance
Operation
Clear ÷2 and ÷5
Increment ÷2
Increment ÷5
Rev.2.00 Mar 30, 2006 page 1 of 6