HD74HC377 Datasheet, PDF (1/7 Pages) Hitachi Semiconductor – Octal D-type Flip-Flops (with Enable)

HD74HC377
Octal D-type Flip-Flops (with Enable)
REJ03D0622-0200
(Previous ADE-205-501)
Rev.2.00
Mar 30, 2006
Description
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse if the enable input G is low. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level,
the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G
input.
Features
• High Speed Operation: t_pd = 13 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC377P
DILP-20 pin
PRDP0020AC-B
P
(DP-20NEV)
HD74HC377FPEL SOP-20 pin (JEITA)
PRSP0020DD-B
(FP-20DAV)
FP
HD74HC377RPEL SOP-20 pin (JEDEC)
PRSP0020DC-A
(FP-20DBV)
RP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
Function Table
Inputs
Outputs
Enable G
Clock
Data
Q
Q
H
X
X
Q0
Q0
L
H
H
L
L
L
L
H
X
L
X
Q0
Q0
Notes: 1. H ; High level, L ; Low level, X ; Irrelevant, _{; Transition from L level to H level.}
2. Q0 ; The level of Q before the indicated steady-state input conditions were established.
3. Q0 ; Complement of Q0 or level of Q before the indicated steady-state input conditions were established.
Rev.2.00 Mar 30, 2006 page 1 of 6