HD74HC164 Datasheet, PDF (1/7 Pages) Hitachi Semiconductor – 8-bit Parallel-out Shift Register

HD74HC164
8-bit Parallel-out Shift Register
REJ03D0580-0300
Rev.3.00
Jan 31, 2006
Description
This 8-bit shift register has gated serial inputs and clear. Each register bit is a D-type master/slave flip-flop. Inputs A
& B permit complete control over the incoming data. A low at either or both inputs inhibits entry of new data and
resets the first flip-flop to the low level at the next clock pulse. A high level on the input enables the other input which
will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or
low, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and
out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and
accomplished by a low level at the clear input.
Features
• High Speed Operation: t_pd (Clock to Q) = 14.5 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC164P
DILP-14 pin
PRDP0014AB-B
(DP-14AV)
P
HD74HC164FPEL SOP-14 pin (JEITA)
PRSP0014DF-B _FP
(FP-14DAV)
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
Function Table
Inputs
Outputs
Clear
Clock
A
B
Q_A
Q_B
·········
Q_H
L
X
X
X
L
L
·········
L
H
X
X
Q_Ao
Q_Bo
·········
Q_Ho
H
L
X
L
Q_An
·········
Q_Gn
H
X
L
L
Q_An
·········
Q_Gn
H
H
H
H
Q_An
·········
Q_Gn
Q_Ao to Q_Ho = Outputs remain unchanged.
Q_An to Q_Gn = Data shifted from the previous stage on a positive edge at the clock input.
H : High level
L : Low level
X : Irrelevant
Rev.3.00, Jan 31, 2006 page 1 of 6