HD74HC137 Datasheet, PDF (1/10 Pages) Hitachi Semiconductor – 3-to-8-line Decoder/Demultiplexer with Address Latch

HD74HC137
3-to-8-line Decoder/Demultiplexer with Address Latch
REJ03D0569-0200
(Previous ADE-205-443)
Rev.2.00
Oct 11, 2005
Description
The HD74HC137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes
from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains
high no address changes will be recognized. Output enable controls, G₁ and G₂, control the state of the outputs
independently of the select or latch-enable inputs.
All of the outputs are high unless G₁ is high and G₂ is low. The HD74HC137 is ideally suited for the implementation of
glitchfree decoders in stored-address applications in bus oriented systems.
Features
• High Speed Operation: t_pd (A, B, C to Y) = 16.5 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 V to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC137P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
HD74HC137FPEL SOP-16 pin (JEITA)
PRSP0016DH-B
(FP-16DAV)
FP
HD74HC137RPEL SOP-16 pin (JEDEC)
PRSP0016DG-A _RP
(FP-16DNV)
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Rev.2.00, Oct 11, 2005 page 1 of 9