HD74HC108 Datasheet, PDF (1/7 Pages) Hitachi Semiconductor – Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)

HD74HC108
Dual J-K Flip-Flops
(with Preset, Common Clear and Common Clock)
REJ03D0560-0200
(Previous ADE-205-433)
Rev.2.00
Oct 11, 2005
Description
This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each
flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are controlled by a common clear
and a common clock. Preset and clear are independent of the clock and accomplished by a low logic level on the
corresponding input.
Features
• High Speed Operation: t_pd (Clock to Q) = 20 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 2 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
PRSP0014DE-A
HD74HC108RPEL SOP-14 pin (JEDEC) _(FP-14DNV)
RP
Taping Abbreviation
(Quantity)
EL (2,500 pcs/reel)
Function Table
Inputs
Outputs
Preset
Clear
Clock
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H*¹
H*¹
H
H
L
L
No change
H
H
L
H
L
H
H
H
H
L
H
L
H
H
H
H
Toggle
H
H
L
X
X
No change
H
H
H
X
X
No change
H
H
X
X
No change
Note: 1. Q and Q will remain High as long as preset and Clear are Low, but Q and Q are unpredictable, if Preset and
Clear go High simultaneously.
H : High level
L : Low level
X : Irrelevant
Rev.2.00, Oct 11, 2005 page 1 of 6