HD74AC280 Datasheet, PDF (1/8 Pages) Hitachi Semiconductor – 9-bit Parity Generator/Checker

HD74AC280
9-bit Parity Generator/Checker
REJ03D0266–0200Z
(Previous ADE-205-387 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC280 is a high-speed parity generator/checker that accepts nine bits of input data and detects whether an
even or an odd number of these inputs is High. If an even number of inputs is High, the Sum Even output is High. If an
odd number is High, the Sum Even output is Low. The Sum Odd output is the complement of the Sum Even output.
Features
• Outputs Source/Sink 24 mA
• Ordering Information
Part Name
Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74AC280FPEL SOP-14 pin (JEITA) FP-14DAV
FP
EL (2,000 pcs/reel)
HD74AC280RPEL SOP-14 pin (JEDEC) FP-14DNV
RP
EL (2,500 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
I6 1
I7 2
NC 3
I8 4
ΣE 5
ΣO 6
GND 7
(Top view)
14 VCC
13 I5
12 I4
11 I3
10 I2
9 I1
8 I0
Rev.2.00, Jul.16.2004, page 1 of 7