HD74AC123A Datasheet, PDF (1/7 Pages) Hitachi Semiconductor – Dual Retriggerable Resettable Multivibrator

HD74AC123A
Dual Retriggerable Resettable Multivibrator
REJ03D0245–0200Z
(Previous ADE-205-365 (Z))
Rev.2.00
Jul.16.2004
Description
Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding
Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth
Table) will cause the delay period to start again, without disturbing the outputs. By repeating this process, the output
pulse period (Q High, Q Low) can be made as long as desired. Alternatively, a delay period can be terminated at any
time by a Low signal on C_D, which also inhibits triggering. An internal connection from C_D to the input gate makes it
possible to trigger the circuit by a positive-going signal on C_D, as shown in the Truth Table. For timing capacitor values
greater than 1000 pF, the output pulse width is defined as follows.
Where t_w is in ns, R_X is in kΩ and C_X is in pF.
t_w = R_XC_X
Features
• Outputs Source/Sink 24 mA
• Ordering Information
Part Name
Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74AC123AP DIP-16 pin
DP-16E, -16FV P
—
HD74AC123AFPEL SOP-16 pin (JEITA) FP-16DAV
FP
EL (2,000 pcs/reel)
HD74AC123ARPEL SOP-16 pin (JEDEC) FP-16DNV
RP
EL (2,500 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
A₁ 1
B₁ 2
C_D1 3
Q₁ 4
Q₂ 5
C_X2 6
R_X2C_X2 7
GND 8
(Top view)
16 V_CC
15 R_X1C_X1
14 C_X1
13 Q₁
12 Q₂
11 C_D2
10 B₂
9 A₂
Rev.2.00, Jul.16.2004, page 1 of 6