HD151012 Datasheet, PDF (1/14 Pages) Hitachi Semiconductor – 8-bit Binary Programmable Counter with Synchronous Preset Enable

HD151012
8-bit Binary Programmable Counter with Synchronous Preset
Enable
REJ03D0299–0200Z
(Previous ADE-205-132 (Z))
Preliminary
Rev.2.00
Jul.16.2004
Description
The HD151012 has 8-bit binary down counter and D-type Flip Flop. The counter can set up to max 256 counts and
synchronous preset (SPE) input can preset the data. When the count value is 0, the next clock pulse presets the data to
invert the output. D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the
rise edge. It is applied to generate AC signal for STN type liquid crystal and general-use divider.
Features
• High speed operation
tpd (CLK or CLK to Q) = 35 ns (typ)
• High output current
Fanout of 10 LS TTL Loads
• Wide operating voltage
V_CC = 2 to 6 V
• Low supply current (Ta = 25°C)
I_CC (Static) = 4 µA (max)
• Ordering Information
Part Name
HD151012TELL
Package Type
TSSOP-16 pin
Package Code
Package
Abbreviation
TTP-16DAV
T
Taping Abbreviation
(Quantity)
ELL (2,000 pcs/reel)
Function Table
Control Inputs
CLR
PR
SPE
Mode
Operation Description
H
H
H
Generally count
Down count at the rise edge of clock (CLK)
Down count at the fall edge of clock (CLK)
X
X
L
Synchronous preset Jn data is preset at the rise of clock (CLK), the fall of clock
(CLK)
L
H
—
Initialize of Q output Initialize of Q = “L”
H
L
—
Initialize of Q output Initialize of Q = “H”
Notes: 1. Synchronous preset (SPE) input can set max 256 down counts.
2. When the count value is 0, the next clock pulse presets the data to invert the output.
3. CLR and PR inputs initialize output state.
H : High level
L : Low level
X : Immaterial
— : Irrespective of condition
Rev.2.00, Jul.16.2004, page 1 of 13