R1120 Datasheet, PDF (2/5 Pages) RDC Semiconductor – 16-BIT RISC MICROCONTROLLER

RDC®
RISC DSP Communication
1. Features
l Five-stage pipeline
l RISC architecture
l Integrated PLL (*1~*8)
l Maximum frequency: 80 MHz; the external bus,
internal bus and core are operating in the same
clock base
l Static & synthesizable design
l Bus interface
- A multiplexed address and data bus which is
compatible with the 80C186 microprocessor
- Supports a direct address bus A[19:0]
- 1M-byte memory address space
- 64K-byte I/O space
l Software is compatible with the 80C186
microprocessor
l Supports two asynchronous serial channels with
hardware handshaking signals
l Supports CPU ID
l Supports 32 PIO pins
l
l
R1120
16-BIT RISC MICROCONTROLLER
l PSRAM (Pseudo static RAM) interface with auto-refresh
control
l Three independent 16-bit timers and one independent
watchdog timer
l The Interrupt controller with seven maskable
external interrupts and one non-maskable external
interrupt
l Two independent DMA channels
l Programmable chip-select logic for memory or I/O
bus cycle decoder
l Programmable wait-state generators
l The I/O pin output is 3.3 volt level and the input
3.3 to 5 volt tolerance.
l 3.3V operation voltage
l Supports serial port/ DMA transfers
l With 8-bit or 16-bit boot ROM bus size
l A green product
l Package Type
- PQFP100 pins & LQFP100 pins
Specifications subject to change without notice, contact your sales representatives for the most update information.
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REV 1.0 Jul. 28 2005