A01AT-100NS-B Datasheet, PDF (1/1 Pages) RCD COMPONENTS INC. – ACTIVE (DIGITAL) DELAY LINES SINGLE, DUAL, TRIPLE, QUAD DELAYS

ACTIVE (DIGITAL) DELAY LINES
SINGLE, DUAL, TRIPLE, QUAD DELAYS
A0 SERIES
RoHS
Term.W is
RoHS
compliant
RESISTORS CAPACITORS COILS DELAY LINES
RCD
A03SAG
1 50NS
RCD
A04AG
1 100NS
Economical cost, prompt delivery!
Wide range of values, 5nS to 500nS
TTL Schottky interfaced
OPTIONS
Opt.T= trailing edge design
Opt. F =fast TTL, H =HCMOS, C =FACT
Opt.A = auto-insertable design
Opt.39 = -40 to +85°C operating temp.
Tighter tolerances, faster rise times
Low power design
Military screening
STANDARD DELAY TIMES
5nS, 10nS, 15nS, 20nS, 25nS, 50nS,
75nS, 100nS, 250nS, 500nS
Intermediate values available on special order.
Low cost solution for multiple timing delays in a single package!
RCD’s digital delay lines have been designed to provide precise fixed delays with all
the necessary drive and pick-off circuitry. All inputs and outputs are Schottky-type
and require no additional components to achieve specified delays. Designed to
meet the applicable environmental requirements of MIL-D-23859. Type A01 features
a single fixed delay, type A02 features two isolated delays, A03 features three
delays, and A04 features 4 delays (single delay SIP available). Application Guide
available.
PACKAGE STYLES
.500 [12.7] Max
.015 [.4]
↓
↑
↑
SIDSEIDVEIEW .295 [7.5]
Max.
↓
.120 [3] Min
→ ←.100 [2.54]
.300 ±.01
[7.62±.25]
.40 [10.2]Max
.300±.01
[7.6±.25]
PACKAGE STYLE 8P (8-Pin DIP)
.500 [12.7] Max
8
5
TOP VIEW
1
4
→← → ←
.020 [.5] .10 [2.54]
.250
[6.35]
.285 [7.24]
←.300 [7.6] →
← .420 [10.67] →
PACKAGE STYLE 8SM (8-Pin SM DIP)
SPECIFICATIONS
Operating Temp: 0 to 70°C
Delay Tol: ±2nS or ±5%, whichever greater
Rise Time: 4nS
Peak Soldering Temp: +230°C
CHARACTERISTICS
RCD
Type
Independent
Delays
A01
Single
A01S Single
A01AG Single
A01SAG Single
A02A Dual
A02SA Dual
A02AG Dual
A02SAG Dual
A03
Triple
A03S Triple
A03AG Triple
A03SAG Triple
A04
Quadruple
A04AG Quadruple
Package
Style
14P
8P
14SM
8SM
14P
8P
14SM
8SM
14P
8P
14SM
8SM
14P
14SM
Circuit
A
B
A
B
C
D
C
D
E
F
E
F
G
G
← .800 [20.3] Max. →
.40 [10.2]Max
SIDE VIEW
↑
.295 [7.5]
↓
Max.
↓
↑
.015 [.4]
.120 [3] Min
←
.600 ± .010
[15.2 ± .25]
→ ←.100
→
[2.54]
.300±.01
[7.6±.25]
PACKAGE STYLE 14P (14-Pin DIP)
← .800 [20.3] Max →
14
8
TOP VIEW
1
→←
.020 [.5]
7
→←
.10 [2.54]
.285 [7.24]
.300
[7.6]
←.300 [7.6] →
← .420 [10.67] →
PACKAGE STYLE 14SM (14-Pin SM DIP)
CIRCUIT SCHEMATICS
Circuit A
14 ^(VCC)
8 (OUT)
DELAY
1 (IN)
7 (GND)
Circuit B
8 (VCC)
5 (OUT)
DELAY
1 (IN)
4 (GND)
Circuit C
14(VCC) 12(OUT) 8(OUT)
Circuit D
8(VCC) 7(OUT) 5(OUT)
DELAY DELAY
1(IN)
5 (IN) 7 (GND)
DELAY DELAY
1(IN) 3 ^(IN) 4(GND)
Circuit E
14(VCC) 12(OUT) 10(OUT)
8 (OUT)
Circuit F
8(VCC) 7(OUT) 6 (OUT) 5 (OUT)
Circuit G
14 (Vcc) 12(OUT) 10(OUT) 9 (OUT) 8(OUT)
DELAY DELAY DELAY
1(IN)
3 (IN)
5 (IN) 7(GND)
DELAY DELAY DELAY
1(IN)
2(IN) 3^(IN) 4(GND)
DELAY DELAY DELAY DELAY
1(IN)
3 (IN)
4(IN) 5 (IN) 7(GND)
TEST CONDITIONS @25°C
1.) Input test pulse voltage: 3.2V
2.) Input pulse width: 50nS or 1.2x the total
delay (whichever is greater)
3.) Input rise time: 2.0nS (0.75V to 2.4V)
4.) Delay measured at 1.5V on leading edge
only with no loads on output (specify opt. T
for trailing edge design)
5.) Supply Voltage (Vcc): 5V
6.) Pulse spacing: 2x pulse width minimum
P/N DESIGNATION:
Type: A01, A01S, A01AG, etc.
A01A
- 100NS - B W
Options: T, H, F, C, A, 39 (leave blank if std.)
Delay Time: 5NS, 10NS, etc.
Packaging: B=Bulk (Magazine tube is standard)
Termination: W= Lead-free, Q= Tin/Lead
(leave blank if either is acceptable)
RCD Components Inc, 520 E.Industrial Park Dr, Manchester, NH, USA 03109 rcdcomponents.com Tel: [phone] Fax: [phone] Email:[e-mail]
FA077 Sale of this product is in accordance with GF-061. Specifications subject to change without notice.
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