FM28V020_11 Datasheet, PDF (5/14 Pages) Ramtron International Corporation – 256Kbit Bytewide F-RAM Memory

chip enable must remain inactive for at least the
minimum precharge time t_PC.
Precharge is also activated by changing the upper
addess A(14:3). The current row is first closed prior
to accessing the new row. The device automatically
detects an upper order address change which starts a
precharge operation, the new address is latched, and
FM28V020 - 32Kx8 F-RAM
the new read data is valid within the t_AA address
access time. Refer to the Read Cycle Timing 1
diagram on page 9. Likewise a similar sequence
occurs for write cycles. Refer to the Write Cycle
Timing 3 diagram on page 11. The rate at which
random addresses can be issued is t_RC and t_WC,
respectively.
Endurance
The FM28V020 is capable of being accessed at least
10¹⁴ times – reads or writes. An F-RAM memory
operates with a read and restore mechanism.
Therefore, an endurance cycle is applied on a row
basis. The F-RAM architecture is based on an array
of rows and columns. Rows are defined by A14-A3
and column addresses by A2-A0. The array is
organized as 4K rows of 8-bytes each. The entire row
is internally accessed once whether a single byte or
all eight bytes are read or written. Each byte in the
row is counted only once in an endurance calculation
if the addressing is contiguous in nature.
The user may choose to store CPU instructions and
run them from a certain address space. The table
below shows endurance calculations for 256-byte
repeating loop, which includes a starting address and
initial access, 7 page mode accesses, and a CE
precharge. The number of bus clocks needed to
complete an 8-byte read transaction is 1+7+1 or 9
clocks. The entire loop causes each byte to
experience only one endurance cycle. F-RAM read
and write endurance is virtually unlimited.
Table 1. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop
Bus Freq Bus Cycle 256-byte Endurance Endurance Years to
(MHz) Time (ns) Transaction Cycles/sec. Cycles/year Reach 10¹⁴
Time (s)
Cycles
10
100
28.8
34,720
1.09 x 10¹²
91.7
5
200
57.6
17,360
5.47 x 10¹¹
182.8
Rev. 2.1
June 2011
Page 5 of 14