VRS51C1000 Datasheet, PDF (4/48 Pages) Ramtron International Corporation – Versa 8051 MCU with 64KB of IAP/ISP Flash

VRS51C1000
Instruction Set
The following table describes the instruction set of the
VRS51C1000. The instructions are function and binary
code compatible with industry standard 8051s.
Table 3: Legend for Instruction Set Table
Symbol
Function
A
Accumulator
Rn
Register R0-R7
Direct
Internal register address
@Ri
rel
Internal register pointed to by R0 or R1 (except MOVX)
Two's complement offset byte
bit
Direct bit address
#data
#data 16
8-bit constant
16-bit constant
addr 16
16-bit destination address
addr 11
11-bit destination address
TABLE 4: VRS51C1000 INSTRUCTION SET
Mnemonic
Description
Arithmetic instructions
ADD A, Rn
Add register to A
ADD A, direct
Add direct byte to A
ADD A, @Ri
Add data memory to A
ADD A, #data
Add immediate to A
ADDC A, Rn
Add register to A with carry
ADDC A, direct
Add direct byte to A with carry
ADDC A, @Ri
Add data memory to A with carry
ADDC A, #data
Add immediate to A with carry
SUBB A, Rn
Subtract register from A with borrow
SUBB A, direct
Subtract direct byte from A with borrow
SUBB A, @Ri
Subtract data mem from A with borrow
SUBB A, #data
Subtract immediate from A with borrow
INC A
Increment A
INC Rn
Increment register
INC direct
Increment direct byte
INC @Ri
Increment data memory
DEC A
Decrement A
DEC Rn
Decrement register
DEC direct
Decrement direct byte
DEC @Ri
Decrement data memory
INC DPTR
Increment data pointer
MUL AB
Multiply A by B
DIV AB
Divide A by B
DA A
Decimal adjust A
Logical Instructions
ANL A, Rn
AND register to A
ANL A, direct
AND direct byte to A
ANL A, @Ri
AND data memory to A
ANL A, #data
AND immediate to A
ANL direct, A
AND A to direct byte
ANL direct, #data AND immediate data to direct byte
ORL A, Rn
OR register to A
ORL A, direct
OR direct byte to A
ORL A, @Ri
OR data memory to A
ORL A, #data
OR immediate to A
ORL direct, A
OR A to direct byte
ORL direct, #data OR immediate data to direct byte
XRL A, Rn
Exclusive-OR register to A
XRL A, direct
Exclusive-OR direct byte to A
XRL A, @Ri
Exclusive-OR data memory to A
XRL A, #data
Exclusive-OR immediate to A
XRL direct, A
Exclusive-OR A to direct byte
XRL direct, #data Exclusive-OR immediate to direct byte
CLR A
Clear A
CPL A
Compliment A
SWAP A
Swap nibbles of A
RL A
Rotate A left
RLC A
Rotate A left through carry
RR A
Rotate A right
RRC A
Rotate A right through carry
Size
(bytes)
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
Instr. Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
Mnemonic
Description
Boolean Instruction
CLR C
Clear Carry bit
CLR bit
Clear bit
SETB C
Set Carry bit to 1
SETB bit
Set bit to 1
CPL C
Complement Carry bit
CPL bit
Complement bit
ANL C,bit
Logical AND between Carry and bit
ANL C,#bit
Logical AND between Carry and not bit
ORL C,bit
Logical ORL between Carry and bit
ORL C,#bit
Logical ORL between Carry and not bit
MOV C,bit
Copy bit value into Carry
MOV bit,C
Copy Carry value into Bit
Data Transfer Instructions
MOV A, Rn
Move register to A
MOV A, direct
Move direct byte to A
MOV A, @Ri
Move data memory to A
MOV A, #data
Move immediate to A
MOV Rn, A
Move A to register
MOV Rn, direct
Move direct byte to register
MOV Rn, #data
Move immediate to register
MOV direct, A
Move A to direct byte
MOV direct, Rn
Move register to direct byte
MOV direct, direct Move direct byte to direct byte
MOV direct, @Ri
Move data memory to direct byte
MOV direct, #data Move immediate to direct byte
MOV @Ri, A
Move A to data memory
MOV @Ri, direct
Move direct byte to data memory
MOV @Ri, #data
Move immediate to data memory
MOV DPTR, #data Move immediate to data pointer
MOVC A, @A+DPTR
Move code byte relative DPTR to A
MOVC A, @A+PC Move code byte relative PC to A
MOVX A, @Ri
Move external data (A8) to A
MOVX A, @DPTR Move external data (A16) to A
MOVX @Ri, A
Move A to external data (A8)
MOVX @DPTR, A Move A to external data (A16)
PUSH direct
Push direct byte onto stack
POP direct
Pop direct byte from stack
XCH A, Rn
Exchange A and register
XCH A, direct
Exchange A and direct byte
XCH A, @Ri
Exchange A and data memory
XCHD A, @Ri
Exchange A and data memory nibble
Branching Instructions
ACALL addr 11
Absolute call to subroutine
LCALL addr 16
Long call to subroutine
RET
Return from subroutine
RETI
Return from interrupt
AJMP addr 11
Absolute jump unconditional
LJMP addr 16
Long jump unconditional
SJMP rel
Short jump (relative address)
JC rel
Jump on carry = 1
JNC rel
Jump on carry = 0
JB bit, rel
Jump on direct bit = 1
JNB bit, rel
Jump on direct bit = 0
JBC bit, rel
Jump on direct bit = 1 and clear
JMP @A+DPTR
Jump indirect relative DPTR
JZ rel
Jump on accumulator = 0
JNZ rel
Jump on accumulator 1= 0
CJNE A, direct, rel
Compare A, direct JNE relative
CJNE A, #d, rel
Compare A, immediate JNE relative
CJNE Rn, #d, rel
Compare reg, immediate JNE relative
CJNE @Ri, #d, rel Compare ind, immediate JNE relative
DJNZ Rn, rel
Decrement register, JNZ relative
DJNZ direct, rel
Decrement direct byte, JNZ relative
Miscellaneous Instruction
NOP
No operation
Rn: Any of the register R0 to R7
@Ri: Indirect addressing using Register R0 or R1
#data: immediate Data provided with Instruction
#data16: Immediate data included with instruction
bit:
address at the bit level
rel:
relative address to Program counter from +127 to –128
Addr11: 11-bit address range
Addr16: 16-bit address range
#d:
Immediate Data supplied with instruction
Size
(bytes)
1
2
1
2
1
2
2
2
2
2
2
2
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
2
3
1
1
2
3
2
2
2
3
3
3
1
2
2
3
3
3
3
2
3
1
Instr. Cycles
1
1
1
1
1
1
2
2
2
2
1
2
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
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