FM16W08 Datasheet, PDF (2/11 Pages) Ramtron International Corporation – 64Kb Wide Voltage Bytewide F-RAM

FM16W08
A0-A12
CE
Address
Latch &
Decoder
A0-A12
8,192 x 8 FRAM Array
WE
Control
Logic
OE
I/O Latch
Bus Driver
DQ0-7
Pin Description
Pin Name
A(12:0)
DQ(7:0)
/CE
/OE
/WE
VDD
VSS
Type
Input
I/O
Input
Input
Input
Supply
Supply
Figure 1. Block Diagram
Description
Address: The 13 address lines select one of 8,192 bytes in the F-RAM array. The
address value is latched on the falling edge of /CE.
Data: 8-bit bi-directional data bus for accessing the F-RAM array.
Chip Enable: /CE selects the device when low. Asserting /CE low causes the
address to be latched internally. Address changes that occur after /CE goes low
will be ignored until the next falling edge occurs.
Output Enable: Asserting /OE low causes the FM16W08 to drive the data bus
when valid data is available. Deasserting /OE high causes the DQ pins to be tri-
stated.
Write Enable: Asserting /WE low causes the FM16W08 to write the contents of
the data bus to the address location latched by the falling edge of /CE.
Supply Voltage
Ground
Functional Truth Table
/CE
/WE
Function
H
X
Standby/Precharge
↓
X
Latch Address (and Begin Write if /WE=low)
L
H
Read
L
↓
Write
Note: The /OE pin controls only the DQ output buffers.
Rev. 1.2
Mar. 2011
Page 2 of 11