EM47FM3288SBA Datasheet, PDF (36/40 Pages) Eorex Corporation – 16Gb (64M×8Bank×32) Double DATA RATE 3 Stack SDRAM

EM47FM3288SBA
Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom
impedance, additive latency, write leveling enable and Qoff. The Mode Register 1 is written by asserting low on
/CS, /RAS, /CAS, /WE, high on BA0, low on BA1 and BA2, while controlling the states of address pins
according to the table below.
BA2 BA1 BA0 A13 A12 A11 A10 A9
0
01
0
Qoff
0
0
Rtt
A8 A7 A6 A5 A4 A3
0
Level Rtt D.I.C
AL
A2 A1 A0
Rtt D.I.C DLL
Qoff
A12
Output buffer enabled 0
Output buffer disabled 1
MRS Mode
MR0
MR1
MR2
MR3
BA1 BA0
0
0
0
1
1
0
1
1
Write leveling enable A7
Disabled
0
Enabled
1
Output Driver
A5 A1
Impedance Control
RZQ/6
00
RZQ/7
01
Reserved
10
Reserved
11
DLL Enable A0
Enable
0
Disable
1
Rtt_Nom
A9
ODT disabled 0
RZQ/4
0
RZQ/2
0
RZQ/6
0
RZQ/12
1
RZQ/8
1
Reserved
1
Reserved
1
A6 A2
00
01
10
11
00
01
10
11
Additive Latency A4 A3
AL disabled
00
CL - 1
01
CL - 2
10
Reserved
11
Note1. BA2, A8, A10 and A13 are reserved for future use (RFU) and must be programmed to 0 during MRS.
Note2. Qoff: Outputs disabled - DQs, DQSs, /DQSs.
Note3. In Write leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 1, all RTT_Nom settings are allowed; in Write
Leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 0, only RTT_Nom settings of RZQ/2, RZQ/4 and
RZQ/6 are allowed.
DLL Enable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon
returning to normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0 =
0), the DLL is automatically disabled when entering self-refresh operation and is automatically re-enabled upon
exit of self-refresh operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must
occur before a read or synchronous ODT command can be issued to allow time for the internal clock to be
synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the
tDQSCK, tAON or tAOF parameters. During tDLLK, CKE must continuously be registered high. DDR3 SDRAM
does not require DLL for any Write operation, except when RTT_WR is enabled and the DLL is required for
Jul. 2012
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