QT300_03 Datasheet, PDF (6/12 Pages) Quantum Research Group – CAPACITANCE TO DIGITAL CONVERTER

4.3 Trigger pulse description
The part wakes from low power mode when the first negative
edge is detected on the 1W pin (Figure 4-1, bottom). The
negative pulse must be at least 30µs wide.
The host then generates the positive pulse that actually sets
the Baud rate. The QT300 measure this pulse and uses its
length to set the Baud bit (shift out) rate. 30µs (or more) of
logic-low must follow this pulse.
The host must then float the 1W line to allow the QT300 to
start the signal acquisition.
5.3 PCB LAYOUT
5.3.1 GROUND PLANES
The use of ground planes around the device is encouraged
for noise reasons, but ground or power should not be
coupled too close to the sense pins in order to reduce Cx
load. Likewise, the traces leading from the sense pins to the
electrode should not be placed directly over a ground plane;
rather, the ground plane should be relieved by at least 3
times the width of the sense traces directly under it, with
periodic thin bridges over the gap to provide ground
continuity.
5 Circuit Guidelines
5.1 Sample capacitors
Cs capacitors can be virtually any plastic film or low to
medium-K ceramic capacitor. The normal usable Cs range is
from 1nF ~ 500nF depending on the sensitivity required;
larger values of Cs require higher stability to ensure low drift.
Acceptable capacitor types include NP0 or C0G ceramic,
PPS film, and Y5E and X7R ceramics in that order.
5.2 Power Supply
5.3.2 NOISE SYNCHRONIZATION
External fields can cause interference leading to a noisy and
unstable signal. The most common external fields usually are
from AC mains power.
The /REQ line of the QT300 can be used to synchronize the
acquisition to a repetitive external source of interference
such as the power line frequency in order to dramatically
reduce signal noise.
If line frequency is present near the sensors, this feature
should be used.
5.2.1 STABILITY
The QT300 makes use of the power supply as a reference
voltage. The acquired signal will shift slightly with changes in
Vdd; Vdd fluctuations often happen when additional loads
are switched on or off such as LEDs etc.
If the power supply is shared with another electronic system,
care should be taken to assure that the supply is free of
spikes, sags, and surges. It is best practice to use a
regulator just for the QT300 (or one for a set of QT300's).
5.2.2 SUPPLY REQUIREMENTS
Vdd can range from 2 to 5 volts nominal. Current drain will
vary depending on Vdd. During writing of the internal
EEPROM, Vdd must be at least 2.2 volts.
If desired, the supply can be regulated using a conventional
regulator, for example CMOS LDO regulators, or standard
78Lxx-series 3-terminal devices.
For proper operation a 100nF (0.1uF) ceramic bypass
capacitor must be used between Vdd and Vss; the bypass
cap should be placed very close to the Vdd and Vss pins.
6 Parameter Setups Cloning
A special interface is provided to allow user-defined Setups
to be loaded into internal eeprom or read back out for
development and production purposes.
The QTM300CA cloning board in conjunction with QT3View
software simplifies the Setups cloning process greatly. The
E3A eval board has been designed with a connector to
facilitate direct connection with the QTM300CA. The
QTM300CA in turn connects to any PC with a serial port
which can run QT3View software (included with the
QTM300CA and available free on Quantum’s web site).
The connections required for cloning are shown in Figure
6-1. Further information on the cloning process can be found
in the QTM300CA instruction guide. The parameters which
can be altered are shown in Table 7-4.
The internal eeprom has a life expectancy of 100,000
erase/write cycles and the minimum voltage for a write cycle
is 2.2 Volts.
A serial interface specification for the device can be obtained
by contacting Quantum.
DRDY
SCK
REQ
SDI
Cloning Signal
Vdd
QT 300
100nF
8
Vcc
1
DRDY
2
3
SCK SNS 1
6
5
REQ SNS 2
CS
7
SDO
GND
4
SENSOR
LQ
Figure 6-1 Clone interface wiring
6
QT300 R1.01 21/09/03