QT60320C Datasheet, PDF (5/14 Pages) Quantum Research Group – 32-KEY QMATRIX CHARGE-TRANSFER IC

dV/dt of the rising edge of an
'X' scan line. The charge is
sampled 'n' times during the
course of a burst of switching
cycles of length 'n'. As the
burst progresses the charge on
Cs increases in a staircase
fashion (Figure 1-4).
At the burst's end the voltage
on Cs, which is on the order of
a few tenths of a volt, is
amplified by a gain circuit
which includes an offset
current from the R2R ladder
DAC driven by the X drive
lines. The offset current from
the R2R ladder repositions the
output of the amplifier chain to
coincide as closely as possible
with the center span of the
60320's ADC, which can
convert voltages between 0
and 5 volts. Between bursts the
Cs reset mosfet is activated to
reset the Cs capacitor to
ground.
Figure 2-1 Basic QT60320 Circuit
V cc
D S 18 11
UART IN
UART OUT
5 17 27 29 38
V V V VV
4 _Rst
9
10 ^Rx
Tx
33
I1
34 _I2
35
36 ^I3
I4
X1 ⁴⁰
41
X2 ₄₂
X3 ₄₃
X4
X5 ⁴⁴
1
X6 ₂
X7
X8 ³
11
12 ^O1
O2
13 _O3
14 _O4
23
24 ^O5
O6
25
O7
26 _O8
8
XT1
7
XT2
8MHz
V cc
CAL LED
15
L1
16
L2
R2R dac 100K
19
YS1
YS2 ²⁰
21
YS3
YS4 ²²
C6 (Cz1) 820pF
32
CC1
C7 (Cz2) 820pF
31
CC2
CS ³⁰
BSN20
37
+
AIN
_
R3 68K
_
+
TL C22 72
STAT LED
GGGG
6 18 28 39
R6 10K
R4 100K
Keymatrix
Y4 Y3 Y2 Y1
R5 10K
C5 (Cs)
1 5nF
74 AC 04
Gain is directly controlled by
burst length 'n', amplifier gain
Av, and the values of Cs, Cz1 and Cz2. Only 'n' can be
adjusted on a key by key basis whereas Av and the
capacitances can only be adjusted for all keys. The amplifier
should typically have a total positive gain of 100 +/- 20%..
If there is a large amount of coupling between X and Y lines,
and where burst length 'n' is set to a high number, charge
accumulation on Cs may reach a point where the ladder DAC
can no longer offset the signal back into the ADC's usable
range. In this case the circuit will employ one or two of the Cz
capacitors to 'knock back' or cancel the charge accumulated
on Cs; each Cz will cancel charge
Figure 2-2 Improved Circuit to Suppress Water Films
in a discrete step as required.
Vcc
D S 18 11
UART IN
UART OUT
5 17 27 29 38
V V V VV
4
R st
9 _Rx
10
Tx
33 _I1
34
35 ^I2
I3
36
I4
40
X2 ⁴¹
X3 ⁴²
43
X4 ₄₄
X5 ₁
X6
X7 ²
3
X8
11
12 ^O1
O2
13 _O3
14
O4
23
24 ^O5
25 ^O6
O7
26 _O8
8 _XT1
7
XT2
8MH z
Vcc
CAL L ED
15 _L1
16 _L2
R2R dac 100K
19
YS1
YS2 ²⁰
21
YS3
22
YS4
C6 (Cz1) 820pF
CC 1 ³²
C 7 (Cz2) 820p F
31
CC 2
30
CS
BS N 20
AIN ³⁷
+
_
22V10
R3 68K
_
+
TLC2272
STAT LED
GGGG
6 18 28 39
R6 10K
R4 100K
Keym atr ix
Y4 Y3 Y2 Y1
E I /O
I/O I /O
I/O
E
E
QS3125
E I /O
I/O I /O
I/O
Ct
Rt
R5 1 0K
C5 (Cs)
15nF
Components shown in Figure 2-1
include:
An LVD reset (e.g. Dallas
DS1811) suitable for 5 volt
supplies and an active-low on
low-voltage output;
An R2R ladder network (CTS
750-107R100K or equivalent);
A >2MHz GBW CMOS rail-rail
output opamp capable of
sensing ground on the inputs;
An 8MHz crystal or resonator,
or a ceramic resonator with
built-in capacitors;
Two indicator LEDs (optional)
to show sensing state and
calibration status;
74AC04 inverters to drive the
two banks of analog switches
in opposite states;
Two 74HC4066 analog
switches;
A reset mosfet, most any
small-signal mosfet with a
guaranteed on-state at 4 volts
LQ
5
QT60320C R1.08/01.03