HYS72T64000HR Datasheet, PDF (62/74 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
Label Code
JEDEC SPD Revision
Byte#
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Description
t_RAS.MIN [ns]
Module Density per Rank
t_AS.MIN and t_CS.MIN [ns]
t_AH.MIN and t_CH.MIN [ns]
t_DS.MIN [ns]
t_DH.MIN [ns]
t_WR.MIN [ns]
t_WTR.MIN [ns]
t_RTP.MIN [ns]
Analysis Characteristics
t_RC and t_RFC Extension
t_RC.MIN [ns]
t_RFC.MIN [ns]
t_CK.MAX [ns]
t_DQSQ.MAX [ns]
t_QHS.MAX [ns]
PLL Relock Time
T_CASE.MAX Delta / ∆T_4R4W Delta
Psi(T-A) DRAM
∆T₀ (DT0)
∆T_2N (DT2N, UDIMM) or ∆T_2Q (DT2Q, RDIMM)
∆T_2P (DT2P)
∆T_3N (DT3N)
∆T_3P.fast (DT3P fast)
∆T_3P.slow (DT3P slow)
∆T_4R (DT4R) / ∆T_4R4W Sign (DT4R4W)
∆T_5B (DT5B)
∆T₇ (DT7)
Psi(ca) PLL
Psi(ca) REG
∆T_PLL (DTPLL)
∆T_REG (DTREG) / Toggle Rate
SPD Revision
HYS72T256020HR–5–A
2 GByte
×72
2 Ranks (×4)
PC2–3200R–333
Rev. 1.1
HEX
28
01
35
47
15
27
3C
28
1E
00
00
37
69
80
23
2D
0F
51
78
33
1D
1E
1B
1E
17
28
1B
1E
C4
8C
59
5C
11
HYS72T256220HR–5–A
2 GByte
×72
2 Ranks (×4)
PC2–3200R–333
Rev. 1.1
HEX
28
01
35
47
15
27
3C
28
1E
00
00
37
69
80
23
2D
0F
51
78
33
1D
1E
1B
1E
17
28
1B
1E
C4
8C
59
5C
11
Rev. 1.31, 2006-11
62
03292006-21GC-MK06