HYS64D32000HDL Datasheet, PDF (4/32 Pages) Qimonda AG – 200-Pin Small-Outline Dual-In-Line Memory Modules

Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
1.2
Description
The HYS64D32000HDL–[5/6]–C and HYS64D64020HDL–
[5/6]–C are industry standard 200-Pin Small-Outline
Dual-In-Line Memory Modules (SO-DIMMs) organized as
64M ×64. The memory array is designed with Double Data
Rate Synchronous DRAMs ( ). A variety of de coupling
capacitors are mounted on the PC board. The DIMMs feature
serial presence detect based on a serial E²PROM device
using the 2-pin I²C protocol. The first 128 bytes are
programmed with configuration data and the second
128 bytes are available to the customer.
Product Type¹⁾
TABLE 2
Ordering Information for Lead-Free (RoHS Compliant Products)
Compliance Code²⁾
Description
SDRAM Technology
PC3200 (CL=3.0)
HYS64D32000HDL–5–C PC3200S-3033–1–C0
One rank 256MB SO-DIMM 512 MBit (×16)
HYS64D64020HDL–5–C PC3200S-3033–1–A0
Two ranks 512MB SO-DIMM 512 MBit (×16)
PC2700 (CL=2.5)
HYS64D32000HDL–6–C PC2700S–2533–1–C0
One rank 256MB SO-DIMM 512 MBit (×16)
HYS64D64020HDL–6–C PC2700S-2533–1–A0
Two ranks 512MB SO-DIMM 512 MBit (×16)
1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example:
HYS64D64020GDL–5–B, indicating Rev.B die are used for SDRAM components.
2) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC3200”), the latencies (for example
“30330” means CAS latency of 3.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Pre-charge latency of 3 clocks), JEDEC
SPD code definition version 1, and the Raw Card used for this module.
Rev. 1.11, 2006-09
4
03292006-428D-USV0