HYS72D64301HBR-5-C Datasheet, PDF (34/39 Pages) Qimonda AG – 184-Pin Registered Double-Data-Rate SDRAM Module

Internet Data Sheet
HYS72D[64/128/256]xxxHBR–[5/6]–C
Registered Double-Data-Rate SDRAM Module
6
Application Note
Power Up and Power Management on DDR Registered DIMMs
(according to JEDEC ballot JC-42.5 Item 1173)
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and to minimize
power consumption during low power mode. One feature is externally controlled via a system-generated RESET signal; the
second is based on module detection of the input clocks. These enhancements permit the modules to power up with SDRAM
outputs in a High-Z state (eliminating risk of high current dissipations and/or dotted I/Os), and result in the powering-down of
module support devices (registers and Phase-Locked Loop) when the memory is in Self-Refresh mode.
The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other SDRAM inputs are
maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low level, all the register outputs are
forced to a low level, and all differential register input receivers are powered down, resulting in very low register power
consumption. The RESET pin, located on DIMM tab #10, is driven from the system as an asynchronous signal according to
the attached details. Using this function also permits the system and DIMM clocks to be stopped during memory Self Refresh
operation, while ensuring that the SDRAMs stay in Self Refresh mode.
Register Inputs
TABLE 16
Function for RESET
Register Outputs¹⁾
RESET
CK
CK
Data in (D)
Data out (Q)
H
Rising
Falling
H
H
H
Rising
Falling
L
L
H
L or H
L or H
X
Qo
H
High Z
High Z
X
Illegal input conditions
L
X or Hi-Z
X or Hi-Z
X or Hi-Z
L
1) X : Don’t care, Hi-Z : High Impedance, Qo: Data latched at the previous of CK risning and CK falling
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are maintained low
at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low maintains a high impedance
state on the SDRAM DQ, DQS and DM outputs — where they will remain until activated by a valid ‘read’ cycle. CKE low also
maintains SDRAMs in Self Refresh mode when applicable.
The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz or greater
is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating frequency at which all
specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual detect frequency will vary by
vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made High-Z, and the differential inputs are
powered down — resulting in a total PLL current consumption of less than 1mA. Use of this low power PLL function makes the
use of the PLL RESET (or G pin) unnecessary, and it is tied inactive on the DIMM.
This application note describes the required and optional system sequences associated with the DDR Registered DIMM
'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2-bank DIMM. Because
RESET applies to all DIMM register devices, it is therefore not possible to uniquely control CKE to one physical DIMM bank
through the use of the RESET pin.
Rev. 1.21, 2006-08
34
03292006-6N25-8R3I