HYS72T512341HHP Datasheet, PDF (21/32 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Product Type
Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B
Registered DDR2 SDRAM Modules
Organization
Label Code
JEDEC SPD Revision
Byte#
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Description
t_RC and t_RFC Extension
t_RC.MIN [ns]
t_RFC.MIN [ns]
t_CK.MAX [ns]
t_DQSQ.MAX [ns]
t_QHS.MAX [ns]
PLL Relock Time
T_CASE.MAX Delta / ∆T_4R4W Delta
Psi(T-A) DRAM
∆T₀ (DT0)
∆T_2N (DT2N, UDIMM) or ∆T_2Q (DT2Q, RDIMM)
∆T_2P (DT2P)
∆T_3N (DT3N)
∆T_3P.fast (DT3P fast)
∆T_3P.slow (DT3P slow)
∆T_4R (DT4R) / ∆T_4R4W Sign (DT4R4W)
∆T_5B (DT5B)
∆T₇ (DT7)
Psi(ca) PLL
Psi(ca) REG
∆T_PLL (DTPLL)
∆T_REG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
4 GByte
4 GByte
4 GByte
×72
×72
×72
4 Ranks (×4)
4 Ranks (×4)
4 Ranks (×4)
PC2–4200P–444 PC2–4200P–444 PC2–4200P–444
Rev. 1.2
Rev. 1.2
Rev. 1.2
HEX
00
3C
69
80
1E
28
0F
50
7A
43
29
36
21
41
2A
40
1E
22
C4
8C
61
78
12
9F
7F
7F
HEX
00
3C
69
80
1E
28
0F
50
7A
43
29
36
21
41
2A
40
1E
22
C4
8C
61
78
12
9F
7F
7F
HEX
00
3C
69
80
1E
28
0F
50
7A
43
29
36
21
41
2A
40
1E
22
C4
8C
61
78
12
9F
7F
7F
Rev. 1.0, 2006-12
21
11032006-VX0M-M6IH