HYS64T32000HU-3-A Datasheet, PDF (21/76 Pages) Qimonda AG – 240-Pin Unbuffered DDR2 SDRAM Modules

Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–667
Min.
Max.
Unit
Notes^1)2)3)4)5)6)
7)8)
Active to active command period for 1KB page t_RRD
size products
Active to active command period for 2KB page t_RRD
size products
Four Activate Window for 1KB page size products t_FAW
Four Activate Window for 2KB page size products t_FAW
CAS to CAS command delay
t_CCD
Write recovery time
t_WR
Auto-Precharge write recovery + precharge time t_DAL
Internal write to read command delay
t_WTR
Internal Read to Precharge command delay
t_RTP
Exit self-refresh to a non-read command
t_XSNR
Exit self-refresh to read command
t_XSRD
Exit precharge power-down to any valid
t_XP
command (other than NOP or Deselect)
7.5
—
10
—
37.5
—
50
—
2
—
15
—
WR + t_nRP
—
7.5
—
7.5
—
t_RFC +10
—
200
—
2
—
ns
28)
ns
28)
ns
ns
nCK
ns
nCK
ns
ns
ns
nCK
nCK
28)
28)
28)
29)30)
28)31)
28)
28)
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
CKE minimum pulse width ( high and low pulse
width)
t_XARD
t_XARDS
t_CKE
2
—
7 – AL
—
3
—
nCK
nCK
nCK
32)
ODT turn-on delay
t_AOND
2
2
nCK
ODT turn-on
t_AON
t_AC.MIN
t_AC.MAX + 0.7 ns
9)33)
ODT turn-on (Power down mode)
t_AONPD
t_AC.MIN + 2
2 x t_CK.AVG + ns
t_AC.MAX + 1
ODT turn-off delay
t_AOFD
2.5
2.5
nCK
ODT turn-off
t_AOF
t_AC.MIN
t_AC.MAX + 0.6 ns
34)35)
ODT turn-off (Power down mode)
t_AOFPD
t_AC.MIN + 2
2.5 x t_CK.AVG + ns
t_AC.MAX + 1
ODT to power down entry latency
t_ANPD
3
––
nCK
ODT to power down exit latency
t_AXPD
8
nCK
Mode register set command cycle time
t_MRD
2
—
nCK
MRS command to ODT update delay
t_MOD
0
12
ns
1)
OCD drive mode output delay
t_OIT
0
12
ns
1)
Minimum time clocks remain ON after CKE
t_DELAY
t_LS + t_{CK .AVG} + ––
ns
asynchronously drops LOW
t_LH
1) For details and notes see the relevant Qimonda component data sheet
2) V_DDQ = 1.8 V ± 0.1V; V_DD = 1.8 V ± 0.1 V. See notes ^5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
Rev. 1.41, 2007-05
21
03292006-EZUJ-JY4S