P4C187 Datasheet, PDF (6/12 Pages) List of Unclassifed Manufacturers – ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS

P4C187/187L
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)⁽⁹⁾
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
TRUTH TABLE
Mode
CE
WE
Standby
H
X
Read
L
H
Write
L
L
Output
High Z
D_OUT
High Z
Power
Standby
Active
Active
Figure 1. Output Load
* including scope and test fixture.
Note:
Due to the ultra-high speed of the P4C187/L, care must be taken when
testing this device; an inadequate setup can cause a normal functioning
part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the V_CC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between V_CC and ground. To avoid signal reflections,
Figure 2. Thevenin Equivalent
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
D_OUT to match 166Ω (Thevenin Resistance).
Document # SRAM111 REV B
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