P93U422 Datasheet, PDF (3/10 Pages) Pyramid Semiconductor Corporation – HIGH SPEED 256 x 4 STATIC CMOS RAM

P93U422
FUNCTIONAL DESCRIPTION
An active LOW write enable (WE) controls the writing/
reading operation of the memory. When chip select one
(CS₁) and write enable (WE) are LOW and chip select two
(CS₂) is HIGH, the information on data inputs (D₀ through
D₃) is written into the addressed memory word and
preconditions the output circuitry so that true data is
present at the outputs when the write cycle is complete.
This preconditioning operation insures minimum write
recovery times by eliminating the “write recovery glitch.”
Reading is performed with chip selct one (CS ₁) LOW, chip
select two (CS₂) HIGH, write enable (WE) HIGH and
output enable (OE) LOW. The information stored in the
addressed word is read out on the noninverting outputs
(O₀ through O₃). The outputs of the memory go to an
inactive high impedance state whenever chip select one
(CS₁) is HIGH, or during the write operation when write
enable (WE) is LOW.
TRUTH TABLE
Mode
Standby
Standby
D_OUT Disabled
Read
Write
CS₂ CS₁ WE OE
LXXX
XHXX
HL XH
HLHL
HL LX
Output
High Z
High Z
High Z
D_OUT
High Z
Notes: H = HIGH
L = Low
X = Don't Care
HIGH Z = Implies outputs are disabled or off. This
condition is defined as high impedance state
for the P93U422.
SWITCHING CHARACTERISTICS (5,6)
Over Operating Range (Commercial and Military)
Parameters
t ⁽⁷⁾
PLH(A)
t ⁽⁷⁾
PLH(A)
t_PZH (CS_1, CS₂)⁽⁸⁾
t_PZL (CS_1, CS₂)⁽⁸⁾
t_PZH (WE)⁽⁸⁾
t_PZL (WE)⁽⁸⁾
t_PZH (OE)⁽⁸⁾
t_PZL (OE)⁽⁸⁾
t_S(A)
t_h(A)
t_S(DI)
t_h(DI)
t_S (CS_1, CS₂)
t_h (CS_1, CS₂)
t_pw(WE)
t_PHZ (CS_1, CS₂)⁽⁸⁾
t_PLZ (CS_1, CS₂)⁽⁸⁾
t_PHZ (WE)⁽⁸⁾
t_PLZ (WE)⁽⁸⁾
t_PHZ (OE)⁽⁸⁾
t_PLZ (OE)⁽⁸⁾
Description
Delay from Address to Output (Address Access Time) (See Fig. 2)
P93U422 _Unit
Min. Max.
35 ns
Delay from Chip Select to Active Output and Correct Data (See Fig. 2)
25 ns
Delay from Write Enable to Active Output and Correct Data (Write Recovery)
(See Fig. 1)
Delay from Output Enable to Active Output and Correct Data (See Fig. 2)
25 ns
25 ns
Setup Time Address (Prior to Initiation of Write) (See Fig. 1)
Hold Time Address (After Termination of Write) (See Fig. 1)
Setup Time Data Input (Prior to Initiation of Write) (See Fig. 1)
Hold Time Data Input (After Termination of Write) (See Fig. 1)
Setup Time Chip Select (Prior to Initiation of Write) (See Fig. 1)
Hold Time Chip Select (After Termination of Write) (See Fig. 1)
Minimum Write Enable Pulse Width (to Insure Write) (See Fig. 1)
5
ns
5
ns
5
ns
5
ns
5
ns
5
ns
20
ns
Delay from Chip Select to Inactive Output (HIGH Z) (See Fig. 2)
30 ns
Delay from Write Enable to Inactive Output (HIGH Z) (See Fig. 1)
Delay from Output Enable to Inactive Output (HIGH Z) (See Fig. 2)
30 ns
30 ns
Document # SRAM102 REV A
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