P4C164L Datasheet, PDF (1/11 Pages) Pyramid Semiconductor Corporation – LOW POWER 8K x 8 STATIC CMOS RAM

P4C164L
LOW POWER 8K x 8
STATIC CMOS RAM
FEATURES
V_CC Current (Commercial/Industrial)
— Operating: 55 mA
— CMOS Standby: 3 µA
Access Times
—80/100 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE , CE and OE
1
2
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—28-Pin 300 and 600 mil DIP
—28-Pin 330 mil SOP
DESCRIPTION
The P4C164L is a 64K density low power CMOS
static RAM organized as 8Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 80 ns and 100 ns are available. CMOS
is utilized to reduce power consumption to a low level.
The P4C164L device provides asynchronous operation
with matching access and cycle times.
Memory locations are specified on address pins A₀ to
A₁₂. Reading is accomplished by device selection (CE₁
low CE₂ high) and output enabling (OE) while write en-
able (WE) remains HIGH. By presenting the address
under these conditions, the data in the addressed memory
location is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE₁ or OE is HIGH or WE or CE₂ is LOW.
Package options for the P4C164L include 28-pin 300 and
600 mil DIP and 28-pin 330 mil SOP packages.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P5, P6), SOP (S5)
TOP VIEW
Document # SRAM116 REV B
Revised June 2007
1