P4C1256L Datasheet, PDF (1/11 Pages) List of Unclassifed Manufacturers – LOW POWER 32K x 8 STATIC CMOS RAM

P4C1256L
LOW POWER 32K x 8
STATIC CMOS RAM
FEATURES
V_CC Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE and OE
Inputs
DESCRIPTION
The P4C1256L is a 262,144-bit low power CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are available. CMOS
is utilized to reduce power consumption to a low level.
The P4C1256L device provides asynchronous opera-
tion with matching access and cycle times. Memory
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—28-Pin 600 mil DIP
—28-Pin 300 mil CERDIP
—28-Pin 300 mil Narrow Body SOP
locations are specified on address pins A to A . Read-
0
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ing is accomplished by device selection (CE and output
enabling (OE) while write enable (WE) remains HIGH.
By presenting the address under these conditions, the
data in the addressed memory location is presented on
the data input/output pins. The input/output pins stay in
the HIGH Z state when either CE or OE is HIGH or WE
is LOW.
Package options for the P4C1256L include 28-pin 600
mil DIP, 28-pin 300 mil CERDIP, and 28-pin 300 mil Nar-
row Body SOP packages.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P6, D5-2), SOP (S11-3)
TOP VIEW
Document # SRAM121 REV E
Revised June 2007
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