P4C1041L Datasheet, PDF (1/11 Pages) Pyramid Semiconductor Corporation – LOW POWER 256K x 16 (4 MEG) STATIC CMOS RAM

FEATURES
Fast Access Time - 55 ns
Low Power Operation
Single 5V±10% Power Supply
2.0V Data Retention
Easy Memory Expansion Using CE and OE Inputs
Fully TTL Compatible Inputs and Outputs
P4C1041L
LOW POWER 256K x 16 (4 MEG)
STATIC CMOS RAM
Advanced CMOS Technology
Fast t_OE
Automatic Power Down when deselected
Packages
– 44-Pin 400 mil TSOP II
DESCRIPTION
The P4C1041L is a 262,144 words by 16 bits high-speed
CMOS static RAM. The CMOS memory requires no clocks
or refreshing, and has equal access and cycle times. In-
puts are fully TTL-compatible. The RAM operates from a
single 5.0V ± 10% tolerance power supply.
Access times of 55 nanoseconds permit greatly enhanced
system operating speeds. CMOS is utilized to reduce
power consumption to a low level.
The P4C1041L device provides asynchronous operation
with matching access and cycle times. Memory locations
a_pr_lie_shs_ep_dec_bi_yfie_dd_eo_vin_cead_sd_er_lee_cs_ts_iop_nin₍s_CA_E0) taonAd_{17o.uRtpeuatdeinngabislinagcc(oO}m_E-)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE or OE is HIGH or WE is LOW.
The P4C1041L comes in a 44-Pin 400 mil TSOP II pack-
age.
Functional Block Diagram
Pin Configuration
Document # SRAM142 REV OR
TSOP II
Revised March 2011