P3C1256L Datasheet, PDF (1/11 Pages) Pyramid Semiconductor Corporation – LOW POWER 32K x 8 STATIC CMOS RAM

FEATURES
V_CC Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70/85
Wide Range Power Supply: 2.7V to 3.6V
Easy Memory Expansion Using CE and OE Inputs
Common Data I/O
P3C1256L
LOW POWER 32K x 8
STATIC CMOS RAM
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
— 28-Pin 600 mil DIP
— 28-Pin 330 mil SOP
— 28-Pin TSOP
DESCRIPTION
The P3C1256L is a 262,144-bit low power CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access and
cycle times. Inputs are fully TTL-compatible. The RAM
operates with a wide range power supply (2.7V to 3.6V).
Access times of 55 ns and 70 ns are available. CMOS is
utilized to reduce power consumption to a low level.
The P3C1256L device provides asynchronous operation
with matching access and cycle times. Memory locations
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while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE or OE is HIGH or WE is LOW.
Functional Block Diagram
Pin ConfigurationS
Document # SRAM143 REV A
DIP (P6), SOP (S11-3)
TOP VIEW
Revised October 2011