P3C1024L Datasheet, PDF (1/10 Pages) Pyramid Semiconductor Corporation – ULTRA LOW POWER 128K x 8 CMOS STATIC RAM

P3C1024L
ULTRA LOW POWER 128K x 8
CMOS STATIC RAM
FEATURES
V Current (Commercial/Industrial)
CC
— Operating: 10mA/12mA
— CMOS Standby: 10µA/10µA
Access Times
—55/70 (Commercial or Industrial)
Single 3.3 Volts ± 0.3V Power Supply
Easy Memory Expansion Using CE CE and OE
1,
2
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 445 mil SOP
—32-Pin TSOP
DESCRIPTION
The P3C1024L is a 1,048,576-bit low power CMOS static
RAM organized as 128Kx8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 3.3V ± 0.3V tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P3C1024L device provides asynchronous opera-
tion with matching access and cycle times. Memory
FUNCTIONAL BLOCK DIAGRAM
locations are specified on address pins A to A . Read-
0
16
ing is accomplished by device selection (CE low and
1
CE₂ high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory lo-
cation is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or
OE
is
HIGH
or
WE
or
CE₂
is
LOW.
The P3C1024L is packaged in a 32-pin TSOP and 445
mil SOP.
PIN CONFIGURATION
SOP (S12)
TOP VIEW
See end of datasheet for TSOP pin configuration.
Document # SRAM132 REV OR
Revised April 2006
1