PCS5I9350 Datasheet, PDF (7/12 Pages) PulseCore Semiconductor – 3.3V 1:10 LVCMOS PLL Clock Generator

November 2006
rev 0.3
AC Electrical Specifications (VCC = 3.3V ± 5%, TA = -40°C to +85°C)¹
PCS5I9350
Parameter
Description
Condition
Min
Typ
Max Unit
f_VCO
VCO Frequency
÷16 Feedback
200
-
500 MHz
12.5
-
31.25
f_in
f_XTAL
f_refDC
t_r, t_f
Input Frequency
Crystal Oscillator Frequency
Input Duty Cycle
TCLK Input Rise/FallTime
÷32 Feedback
Bypass mode
(PLL_EN = 0)
0.8V to 2.0V
÷2 Output
6.25
-
15.625 _MHz
0
-
200
10
-
25 MHz
25
-
75
%
-
-
1.0
nS
100
-
200
f_MAX
Maximum Output Frequency
÷4 Output
50
-
125 MHz
÷8 Output
25
-
62.5
DC
t_r, t_f
t_sk(O)
t_sk(B)
t_{PLZ, HZ}
t_{PZL, ZH}
BW
Output Duty Cycle
f_MAX < 100MHz
f_MAX > 100MHz
47.5
-
52.5
%
45
-
55
Output Rise/Fall times
0.8V to 2.4V
0.1
-
1.0
nS
Output-to-Output Skew
Banks at same voltage
-
-
150
pS
Bank-to-Bank Skew
Banks at different voltages
-
-
350
pS
Output Disable Time
-
-
10
nS
Output Enable Time
-
-
10
nS
÷16 Feedback
PLL Closed Loop Bandwidth (–3dB)
÷32 Feedback
-
0.7 – 0.9
-
MHz
-
0.6 – 0.8
-
t_JIT(CC)
Cycle-to-Cycle Jitter
Same frequency
Multiple frequencies
-
-
150
pS
-
-
250
t_JIT(PER)
Period Jitter
Same frequency
Multiple frequencies
-
-
100
pS
-
-
150
t_LOCK
Maximum PLL Lock Time
-
-
1
mS
Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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